1. Field of the Invention
The present invention relates to a method of making a semiconductor device and, more particularly, to a method for forming different gate oxide layers in a single chip.
2. Description of Related Art
Recent trends toward high density integrated circuits increase the chip density while decreasing the size of the transistor built on the chip and decreasing gate oxide thickness.
FIG. 1 schematically shows the relationship between the electrical field (MV/cm) and the gate oxide thickness (.ANG.) for a high voltage logic device and a normal voltage logic device. As can be seen, the probability of gate oxide breakdown increases with a decrease in gate oxide thickness. To avoid this problem, supply voltage (V.sub.DD), which is required to operate the chip, has been reduced. Since a reduced supply voltage causes degradation of power and speed, the thickness of the gate oxide layer has to be reduced to cope with this degradation of power and speed.
It is well known that transistor characteristics can be increased by reducing the gate oxide thickness, while at the same time keeping the supply voltage at a constant level. On the other hand, the power consumption can be reduced by decreasing the supply voltage, while keeping the gate oxide thickness at a constant level. Therefore, the gate oxide thickness must be reduced without breakdown thereof, while keeping a constant electric field. This phenomenon is commonly referred to as the "constant electric field scaling law."
It is a recent trend in the DRAM or MDL industry to increase the chip areas occupied by the cell array. Therefore, if the gate oxide layers are formed to have the same thickness throughout the single chip, the gate oxide at the cell array region is subject to suffering from breakdown. Furthermore, since voltage (V.sub.HDD) exceeding supply voltage (V.sub.DD) is supplied to the cell array interior, the electric field applied thereto is increased, and this intensifies or increases the possibility of the gate oxide breakdown.
Since the cell density in the cell army region increases four folds per one generation, controlled threshold voltage is required against sub-threshold leakage and gate length variation, i.e., short channel effect margin is required. Besides short channel margin, drain saturation current (I.sub.DSAT) is required to be increased in the peripheral region.
To overcome some of the above-mentioned problems, several methods have been disclosed. One of them is to increase the doping concentration in the channel region so as to adjust the threshold voltage considering the short channel effect. The increase in the doping concentration, however, decreases the breakdown margin and increases the threshold voltage variation for a given gate length. In other words, gate length margins are reduced.
Another approach is to fabricate the cell array region and peripheral region on different chips, and not on a single chip. This method, however, has a disadvantage of requiring process complexity and is not compatible with low-cost fabrication.